The present invention relates in general to charge pumps and, more particularly, to a charge pump in a phase lock loop.
A conventional phase lock loop (PLL) generally includes a phase detector for monitoring a phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO). The phase detector generates an up control signal and a down control signal for a charge pump to charge and discharge a loop filter at the input of the VCO. The loop voltage developed across the loop filter determines the output frequency of the VCO. The up and down control signals drive the VCO to maintain a predetermined phase relationship between the signals applied to the phase detector, as is well understood.
The charge pump of the prior art PLL may include a p-channel charging transistor and an n-channel discharging transistor serially coupled between a positive power supply conductor (5.0 volts) and ground potential. A resistor, say 60K ohms, is connected between the interconnection of the drains of the p-channel and n-channel transistors and the loop filter for sourcing and sinking current thereto. The current flowing through the charging transistors is proportional to their drain-source potential (V.sub.DS), according to a well known relationship. Unfortunately, the current from the charging transistors becomes non-symmetrical when the loop voltage is less than about 1.6 or greater than 3.0 volts. For example, if the charge pump receives an up control signal to charge the loop filter and the loop voltage is driving the VCO with, say 1.0 volt, the V.sub.DS of the p-channel transistor is 5.0-1.0=4.0 volts. Alternatively, if the charge pump receives a down control signal to discharge the loop filter while the loop voltage is 1.0 volt, the V.sub.DS of the n-channel transistor is 1.0-0.0=1.0 volt. The difference in V.sub.DS of the p-channel and n-channel transistors given the same loop voltage causes non-symmetrical charging and discharging currents.
A similar problem occurs with the up and down control signals when the loop voltage is operating at a high voltage. In this case, the V.sub.DS of the n-channel transistor is greater than the V.sub.DS of the p-channel transistor given the same loop voltage. Again, the non-symmetrical charging current as a function of the up and down control signals and loop voltage tends to produce a non-linear change in loop voltage. Thus, while the frequency versus loop voltage is approximately linear between say 1.6 volts and 3.0 volts, it becomes non-linear between 0.0 to 1.6 volts and between 3.0 and 5.0 volts. The non-symmetrical charging current from the charge pump makes achieving phase lock more difficult in PLLs.
Hence, a need exists for a charge pump in a PLL for providing a linear charging current to the loop filter independent of loop voltage.